Magnetic random access memory (MRAM) using magnetic tunnel junctions (MTJs) is a strong candidate for providing a dense and fast non-volatile storage solution for future memory applications. Conventional MTJ (or magnetoresistive (MR) element) includes at least a pinned ferromagnetic layer and a free ferromagnetic layer separated from each other by a thin tunnel bather layer. The free layer has a reversible magnetization direction that can have two stable directions which are parallel or anti-parallel to a fixed magnetization direction of the pinned layer. Resistance of the MTJ depends on the mutual orientation of the magnetization directions in the free and pinned layers and can be effectively controlled by an external magnetic field, a spin-polarized current or their combination.
A typical MRAM device includes an array of memory cells, a plurality of parallel word lines extended along columns (or rows) of the array, and a plurality of parallel bit lines extended along rows (or columns) of the memory cells. The word and bit lines overlay each other but spaced from each other in a vertical direction. Each memory cell is located at a cross point of a word line and a bit line, and typically includes a single MTJ connected in series with a selection metal-oxide-semiconductor (MOS) transistor. The connected in series MTJ and selection transistor are electrically coupled to the word line at one terminal and to the bit line at the opposite terminal.
FIG. 1 shows a memory cell 10 according to a prior art disclosed in U.S. Pat. No. 7,668,005 (Ueda). The cell 10 includes a magnetic tunnel junction (MTJ) connected in series with a MOS transistor (MOST). The MTJ includes a pinned ferromagnetic layer 12 with a fixed magnetization direction (shown by a solid arrow), a free ferromagnetic layer 16 having a reversible magnetization direction (shown by dashed arrows), and a tunnel barrier layer 14 disposed between the ferromagnetic layers 12 and 16. The MTJ is electrically coupled to a bit line BL at a first end and to a drain (or source) terminal (or region) 23 of the transistor MOST at a second end by means of a conductive stud (or contact) 26. A source (or drain) terminal (or region) 22 of the transistor MOST is coupled to a source line (SL) through a conductive stud (or contact) 25. A gate terminal 27 of the transistor is coupled to a word line (WL). The gate terminal is electrically isolated from the MOST transistor by a thin gate insulator 24. The transistor is formed on a substrate 21 that can be made of a single crystal semiconductor material such as silicon (Si), germanium (Ge), GaAs, SiC or similar.
Use of the MOS transistor as a selection element can limit an arrangement of the existing MRAM and similar nonvolatile memories such resistive RAM (RRAM), phase change RAM (PCRAM) and others into high density three-dimensional design due to long interconnects between memory elements and a selection transistor. Moreover, the three-dimensional MOS technology is relatively expensive. The present application addresses the above problems.